FIG. 35 is a sectional view of a conventional semiconductor device disclosed in IEEE Transactions on Electron Devices, Vol. 42, No. 8 (August 1995).
Referring to FIG. 35, the semiconductor device includes a silicon wafer 101, a buried oxide film 102 formed on the silicon wafer 101, active regions 103a and 103b formed on the buried oxide film 102, and an element isolating region 104 for electrically isolating a plurality of active regions formed on the buried oxide film 102 from each other. The element isolating region 104 is formed by locally oxidizing a SOI layer formed on the buried oxide film 102, which will be described later.
Shown also in FIG. 35 are a gate insulating film 105 formed on the active regions 103a and 103b, a gate electrode 106a containing a p-type impurity and formed over the active region 103a, a gate electrode 106b containing an n-type impurity and formed on the active region 103b, a silicon nitride film 107 covering the gate electrodes 106a and 106b and the element isolating region 104, an interlayer insulating film 108a deposited on the silicon nitride film 107, through holes 109 for electrically connecting the active regions 103a and 103b to first metal conductive leads 110 formed on the interlayer insulating film 108a, an interlayer insulating film 108b formed over the first metal conductive leads 110, through holes 111 for electrically connecting the first metal conductive leads 110 to second metal conductive leads 112 formed on the interlayer insulating film 108b, and a silicon nitride film 113 covering the second metal conductive leads 112.
The active regions 103a and 103b form source/drain regions and channel regions for a p-channel transistor and an n-channel transistor, respectively.
A method of manufacturing the semiconductor device of FIG. 35 will be described hereinafter.
First, as shown in FIG. 36, a silicon nitride film 115 of a predetermined pattern is formed on a SOI wafer which is formed by sequentially depositing the buried oxide film 102 and a SOI layer 114 in that order on the silicon wafer 101. The silicon nitride film 115 has portions extending over regions corresponding to the active regions 103a and 103b and having dimensions corresponding to the design dimensions of the active regions.
Then as shown in FIG. 37, the surface of the SOI layer 114 is oxidized by thermal oxidation using the silicon nitride film 115 as an oxidation mask to form a first LOCOS film 116.
Then, as shown in FIG. 38, portions of the first LOCOS film 116 are removed selectively by wet etching to form a groove 114a in a region of the SOI layer 114 corresponding to an element isolating region.
Then, as shown in FIG. 39, a silicon nitride film 116 is deposited on the side surfaces of the groove 114a.
Then, as shown in FIG. 40, a portion of the surface of the SOI layer 114 forming the bottom surface of the groove 114a is oxidized by thermal oxidation to form a second LOCOS film , i.e., an element isolating region 104. Since a portion of the SOI layer 114 under the groove 114a is oxidized completely, the bottom of the element isolating region 104 is in contact with the upper surface of the buried oxide film 102. The active regions 103a and 103b of the SOI layer 114 are electrically isolated from each other by the element isolating region 104.
Then, the silicon nitride films 115 and 116 used as oxidation masks are removed selectively, and the gate insulating film 105 is formed over the surfaces of the active regions 103a and 103b.
Then, as shown in FIG. 41, polycrystalline silicon films respectively containing a p-type impurity and an n-type impurity are deposited on the gate insulating film 105 over the active regions 103a and 103b, respectively, and the polycrystalline silicon films are patterned to form the gate electrodes 106a and 106b of transistors.
Then, as shown in FIG. 42, source/drain regions are formed in the active regions 103a and 103b by ion implantation, and the entire surface of this structure is covered with a silicon nitride film 107 of a predetermined thickness. Then, side walls 117 of polycrystalline silicon containing an n-type impurity are formed over the side surfaces of the gate electrodes 106a and 106b.
Then, as shown in FIG. 43, the interlayer insulating film 108a and the through holes 109 are formed.
Then, as shown in FIG. 35, the first metal conductive leads 110 are formed on the interlayer insulating film 108a, and the interlayer insulating film 108b is formed over the entire surface of this structure. Then, through holes 111 are formed so as to correspond to the first metal conductive leads 110, and the second metal conductive leads 112 are formed on the second interlayer insulating film 108b so as to be electrically connected to the through holes 111 to complete the semiconductor device shown in FIG. 35.
Thus, the SOI layer 114 is subjected to LOCOS processing twice when manufacturing the conventional semiconductor device to form the electrically isolated active regions 103a and 103b in the SOI layer 114.
The first LOCOS process forms the first LOCOS film 116 of an ordinary type using the silicon nitride film 115 as a mask as shown in FIG. 37. When the oxidation mask has a pattern of a size equal to the design size of the active regions 103a and 103b, bird's beaks are formed due to the lateral oxidation of the active regions 103a and 103b and, consequently, the effective size of the active regions 103a and 103b in a final state are smaller than the design size.
The silicon nitride film 116 is formed as an oxidation mask on the side surfaces of the groove 114a for the second LOCOS process shown in FIG. 39. Thus, bird's beak encroachment is suppressed when forming the LOCOS film 104.
In the conventional technique as stated above, bird's beaks formed when the ordinary LOCOS film is formed by the first LOCOS process are reflected on the final LOCOS film 104. Consequently, the active regions 103a and 103b for forming transistors have portions affected by bird's beaks, and the effective channel width is smaller than the design channel width.
The prior art technique forms the silicon nitride film 115 as the oxidation mask in contact with the surface of the SOI layer 114, forming the LOCOS film 116 by the first LOCOS process as shown in FIG. 37. However, defects are liable to develop in the crystal structure in the subsequent oxidation process, wherein the LOCOS process is carried out with the SOI layer in contact with the silicon nitride film.
The silicon nitride film 116 is formed so as to cover the side surfaces of the groove 114a formed in the SOI layer 114 as the oxidation mask for the second LOCOS process as shown in FIG. 39. Hence, portions of the oxidation mask corresponding to the edges of the silicon oxide film 115 of a uniform thickness, to which the edges of the silicon nitride film 116 are joined, has an increased thickness, so that the growth of bird's beaks can be suppressed. However, a comparatively high stress is induced in portions of the SOI layer near the silicon nitride film 116 causing defects to develop in the crystal structure, which causes the leakage of currents from the transistors.